Flash memory is non-volatile computer memory that can be electrically erased and reprogrammed. Flash memory is primarily used in memory cards and USB flash drives for general storage and transfer of data between computers and other digital products. Flash memory is a specific type of EEPROM (Electrically Erasable Programmable Read-Only Memory) that is erased and programmed in large blocks. Example applications include data storage for PDAs (personal digital assistants), laptop computers, digital audio players, digital cameras and mobile phones. Other applications include game consoles, where flash memory can be used instead of EEPROMs or battery-powered SRAM for game save data.
NAND type flash memory is one of two types of flash memory technologies (the other being NOR) that are currently available. NAND type flash memory is best suited for use in flash devices requiring high capacity data storage. NAND type flash memory offers significant storage space and offers faster erase, write, and read capabilities as compared to NOR type flash memory. FIGS. 1-4 show schematic, layout and cross sectional illustrations respectively of a memory cell string that is a part of a conventional NAND type flash memory device.
FIG. 1 shows a schematic representation of a NAND string 100 that features a conventional select gate structure. In FIG. 1 NAND string 100 has a defined number of wordlines 101 (16, 32, or 64 depending on product design) disposed between a “drain select gate” 103 at one end of the string structure and a “source select gate” 105 at the other end of the string structure. In the NAND string shown in FIG. 1, wordlines 101 include first wordline 107, last wordline 109 and internal wordlines 111. Drain select gate 103 is used to select wordlines 111 during read, program and erase operations. Drain select gate 103 must be a low leakage device such that, for example during read operations, leakage current that can be difficult to distinguish from memory cell current can be reduced (during programming the low leakage drain select gate can prevent the discharge of cells). Conventional NAND string 100 possesses features that affect its operation such as a significant difference in the pitch that exists between its select gates 103 and 105 and its first and last wordlines 107 and 109 (which is the same) and the pitch that exists between individual wordlines of internal wordlines 111.
FIG. 2 shows a layout view 200 of NAND string 100 shown in FIG. 1 that illustrates some of the spacing relationships that are featured by NAND string 100. FIG. 2 shows in addition to elements shown in FIG. 1 spacing 203, between internal wordlines 111, and spacing 205, between first and last wordlines 107 and 109 and adjacent select gates 103 and 105. Referring to FIG. 2, it should be appreciated that due to a the need to suppress hot carrier injection that can cause disturbs during write operations, the spacing 205 between the first and last wordlines 107 and 109 and their adjacent select gates 103 and 107, is formed to be much larger, e.g., 90-100 nm, than the spacing 203 between internal wordlines 111 that are located between the first and last wordlines 107 and 109 of NAND string 100 (e.g. spacing between first and second wordline, third and fourth wordline, etc.). It should be appreciated that the 90 nm-100 nm space between first and last wordlines 107 and 109 and their adjacent select gates must be maintained even when the space between internal wordlines is scaled down from 45 nm (e.g., 32 nm, 22 nm, etc.).
FIG. 3 shows a cross sectional view of NAND string 100 shown in FIG. 2 sectioned along a core source drain direction that further illustrates the component spacing relationships featured by NAND string 100. FIG. 3 shows in addition to elements shown in FIGS. 1 and 2, components of the source-drain junction 301. Referring to FIG. 3, as discussed with reference to FIG. 2, NAND string 100 features a much larger spacing 205 between first and last wordlines 107 and 109 and their adjacent select gates 103 and 105 than the spacing 203 between internal wordlines 111. It should be appreciated that the aforementioned difference in the length of the space that exists between the first and last wordlines 107 and 109 and their adjacent select gates 103 and 105 and the length of the space that exist between the internal wordlines 111 of NAND string 100 has a deleterious affect on the bias conditions of NAND string 100 as is discussed below with reference to FIG. 4.
FIG. 4 illustrates deleterious aspects of bias conditions of conventional NAND string 100 during memory cell erase operations. Referring to FIG. 4, first word line 107 and last word line 109 are situated between neighboring wordlines 405 and 407 and neighboring select gates 103 and 105. As shown in FIG. 4, during erase operations, neighboring wordlines 405 and 407 are biased at the same potential as are first and last wordline 107 and 109, while neighboring select gates 103 and 105 are floated. During erase, the electrical environment that first and last wordlines 107 and 109 are subjected to is impacted by not only the floating gates but electrical coupling from the associated P-well (not shown) that can cause fringing (labeled “X” in FIG. 4) that weakens the electric field that is applied to the first and last wordlines 107 and 109. This condition can result in a much slower erase rate for cells associated with the first and last wordlines 107 and 109 than for cells associated with internal wordlines 111. These differences in erase rates serve to degrade the operation of the associated memory device.
The above discussed erase rate differences are traceable to the non-uniformity of the electric field on one side of first and last wordlines 107 and 109 that is attributable to the factors discussed above. Moreover, it should be appreciated that the erase voltage that is applied via select gate 103 during erase operations is global in nature which results in the same voltage being applied to all wordlines. Thus, to enable first and last wordlines 107 and 109 to pass erase verify, the internal wordlines 111 will need to be significantly over-erased to compensate for the slower erase rate of first and last wordlines 107 and 109. Although, NAND architecture is more forgiving of memory cell over erasure than some other types of memory, significant memory cell over erasure can lead to reliability issues after cycling. It should be appreciated that placing the select gates closer to the wordlines in the conventional design only aggravates the above discussed problems.
A consequence of the large spacing that exists between first and last wordlines 107 and 109 and their neighboring select gates 103 and 105 is manifested in the fab-out Vt of first and last wordlines 107 and 109. More specifically, as a result of the large spacing between first and last wordlines 107 and 109 and their neighboring select gates 103 and 105, the fab-out Vt of first and last wordlines 107 and 109 may be significantly different from the fab-out Vt of the internal word lines 111. Accordingly, the operating characteristics of the transistors that are associated with first and last wordlines 107 and 109 are different from the operating characteristics of the transistors associated with internal wordlines 111. It should be appreciated that the transistors that perform poorest can cause a significant expenditure of operating margin and thus must be compensated for.
A conventional approach to remedying the above discussed fab-out Vt differences is to make the physical length of first and last wordlines 107 and 109 different from the physical length of the internal wordlines 111 using photolithography processes. One such photolithography process is optical proximity correction (OPC). However, optical proximity correction cannot assure uniform Vt distribution from the wordlines in the NAND string after electrical erase. Accordingly, such attempts to compensate for differences in transistor operating characteristics do not avoid the loss of some margin.
Other consequences of the large spacing between the first and last wordlines 107 and 109 of a NAND string 100 and their neighboring select gates 103 and 105 relate to NAND string processing. In particular, to double patterning photolithography processes. It should be appreciated that double patterning photolithography can be an issue as double patterning photolithography may be required to achieve sub-lithographic component dimensions. Double patterning photolithography allows printing at dimensions below that which ordinary photolithography can achieve (e.g., below 45 nm). However, the non-uniform poly spacing show in FIG. 4 between the select gates 103 and 105 and first and last wordlines 107 and 109 of NAND string 100 are very difficult to manage using double patterning photolithography. Consequently, a patterning technique that may be critical to the achievement of smaller device dimensions can be complicated because of the larger spacing that exists between the select gates 103 and 105 and the first and last wordlines 107 and 109 of a conventional NAND string 100 as compared to that which exists between each of the internal wordlines 111 of the conventional NAND string 100.
As is clear from the above discussion, features of the design of conventional NAND strings affect both their fabrication and performance. Moreover, conventional techniques for addressing these problems are unsatisfactory as they can result in reliability problems, can aggravate existing problems and do not avoid the loss of margin.